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w83194br - 39b step - less 3 - dimm cl ock publication release date: june 2000 - 1 - revision 0.46 1.0 general descrip tion the w83194br - 39b is a clock synthesizer which provides all clocks required for high - speed risc or cisc microprocessor such as intel pentium ii or pentium iii. w83194br - 39b provides 64 cpu/pci frequencies which are selectable with smooth transitions by hardware or software. w83194br - 39b also provides 13 sdram clocks controlled by the none - delay buffer_in pin. the w83194br - 39b provides step - less frequency programming by controlling the vco freq. and the programmable pci clock output divisor ratio. a watch dog timer is quipped and when time out, the reset# pin will output 4ms pulse signal. the w83194br - 39b accepts a 14.318 mhz reference crystal as its input. spread spectrum built in at 0.5% or 0.25% to reduce emi. programma ble stopping individual clock outputs and frequency selection through i 2 c interface. the device meets the pentium power - up stabilization, which requires cpu and pci clocks be stable within 2 ms after power - up. using dual function pin for the slots(isa, pc i, cpu, dimm) is not recommend. 2.0 product feature s supports pentium ? ii and !!! cpu with i 2 c. 2 cpu clocks (one free - running cpu clock) 13 sdram clocks for 3 dimms 6 pci synchronous clocks one ioapic clock for multiprocessor support optional single or mixed supply: (vddq1=vddq2 = vddq3 = vddq4 = vddl1 =vddl2= 3.3v) or (vddq1= vddq2 = vddq3=vddq4 = 3.3v, vddl1 = vddl2 = 2.5v) < 250ps skew among cpu and sdram clocks < 250ps skew among pci clocks < 5ns propagation delay sdram from buffer input skew from cpu (earlier) to pci clock 1 to 4ns, center 2.6ns. smooth frequency switch with selections from 66 mhz to 200 mhz cpu step - less frequency programming by controlling the vco freq. and the clock output divisor ratio i 2 c 2 - wire serial interfac e and i 2 c read back 0.25% or 0.5% spread spectrum function to reduce emi in freq. table mode programmable spread spectrum in the m/n step - less mode programmable registers to enable/stop each output and select modes mode pin for power management reset # out when watch dog timer time out one 48 mhz for usb & one 24 mhz for super i/o
w83194br - 39b preliminary publication release date: june 2000 - 2 - revision 0.46 48 - pin ssop package 3.0 pin configurati on 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddq1 * pd#/ref0^ vss xin xout vddq2 pciclk_f/mode0* pciclk0^/fs3& vss pciclk1^ pciclk2^ pciclk3^ pciclk4 vddq2 buffer in vss sdram11 sdram10 vddq3 sdram 9 sdram 8 vss sdata* sdclk* vddl1 ioapic ref1/fs2* vss cpuclk_f cpuclk1 vddl2 reset$ sdram12 vss sdram 0 sdram 1 sdram 2 vddq3 sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vddq4 vddq3 48mhz/fs0* 24mhz/fs1* * :internal 120k pull-high &:internal 120k pull-down ^ :1.5x strength #: active low $ :open drain 4.0 pin description in - input out - output i/o - bi - directional pin # - active low
w83194br - 39b preliminary publication release date: june 2000 - 3 - revision 0.46 & - internal 120k w p ull - down * - internal 120k w pull - up 4.1 crystal i/o symbol pin i/o function xin 4 in crystal input with internal loading capacitors and feedback resistors. xout 5 out crystal output at 14.318mhz nominally. 4.2 cpu, sdram, pci, ioapic clock outputs symbol pin i/o function cpuclk_f 44 out free running cpu clock. not affected by pd# cpuclk1 43 out low skew (< 250ps) clock outputs for host frequencies such as cpu, chipset and cache. powered by vddl2. low if pd# is low. reset# 41 od reset# (open d rain, 4ms low active pulse when watch dog time out) ioapic 47 out high drive buffered output of the crystal, and is powered by vddl1. sdram [ 0:12] 17,18,20,21,28 ,29,31,32,34, 35,37,38,40 out sdram clock outputs. fanout buffer outputs from buffer in pin. (controlled by chipset) pciclk_f/ *mode0 7 i/o free running pci clock during normal operation. latched input. *mode0=1, pin 2 is ref0; *mode0=0, pin2 is pd# pciclk0^/fs3& 8 i/o low skew (< 250ps) pci clock outputs. latched input for fs3 a t initial power up for h/w selecting the output frequency of cpu and pci clocks. pciclk [1:3]^ pciclk 4 10,11,12,13 out low skew (< 250ps) pci clock outputs. pciclk 0:3 are double strength pins pciclk 4 is not. buffer in 15 in inputs to fa nout for sdram outputs.
w83194br - 39b preliminary publication release date: june 2000 - 4 - revision 0.46 4.3 i 2 c control interface symbol pin i/o function sdata* 23 i/o serial data of i 2 c 2 - wire control interface sdclk* 24 in serial clock of i 2 c 2 - wire control interface 4.4 fixed frequency outputs symbol pin i/o function ref 0^ / pd# 2 i/o 14.318mhz reference clock. this ref output is the stronger buffer for isa bus loads.(pin7 *mode0=1) halt all clocks at logic 0 level, when input low (pin7 *mode0=0) ref1 / fs2* 46 i/o 14.318mhz reference clock. latched input for fs2 at ini tial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 24mhz / fs1* 25 i/o 24mhz output clock. latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 48mhz / fs0* 26 i/o 48mhz output for usb during normal operation. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 4.5 power pins symbol pin function vddq1 1 power supply for ref [0:1] crystal and core logic. vddl1 48 power supply for ioapic output, either 2.5v or 3.3v. vddl2 42 power supply for cpuclk[0:3], either 2.5v or 3.3v. vddq2 6, 14 power supply for pciclk_f, pciclk[0:4], 3.3v. vddq3 19, 30, 36 power supply for sdram[0:12], and cpu pll core, nomin al 3.3v. vddq4 27 power for 24 & 48mhz output buffers and fixed pll core. vss 3,9,16,22,33,39,45 circuit ground.
w83194br - 39b preliminary publication release date: june 2000 - 5 - revision 0.46 5.0 frequency by ha rdware fs3 fs2 fs1 fs0 cpu(mhz) sdram(mhz) pci(mhz) 0 0 0 0 80.00 80.00 40.00 0 0 0 1 75.00 75.00 37.50 0 0 1 0 83.30 83.30 41.65 0 0 1 1 66.82 66.82 33.41 0 1 0 0 103.00 103.00 34.33 0 1 0 1 112.00 112.00 37.34 0 1 1 0 68.01 68.01 34.01 0 1 1 1 100.23 100.23 33.41 1 0 0 0 120.00 120.00 30.00 1 0 0 1 115.00 115.00 38.33 1 0 1 0 120.0 0 120.00 40.00 1 0 1 1 105.00 105.00 35.00 1 1 0 0 140.00 140.00 35.00 1 1 0 1 155.00 155.00 38.75 1 1 1 0 124.00 124.00 31.00 1 1 1 1 133.30 133.30 33.30
w83194br - 39b preliminary publication release date: june 2000 - 6 - revision 0.46 6.0 mode pin - power management input co ntrol mode0, pin7 (latche d input) pin 2 0 pd# (input) 1 ref0 (output) 7.0 function descri ption 7.1 2 - wire i 2 c control interface the clock generator is a slave i 2 c component which can be read back the data stored in the latches for verification. all proceeding bytes must be sent to change one of the control bytes. the 2 - wire control interface allows each clock output individually enabled or disabled. on power up, the w83194br - 39binitializes with default register settings. use of the 2 - wire control interface is then opti onal. the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high during normal data transfer. there are only two exceptions. one is a high - to - low transition on sdata while sdclk is high used to indicate the beginning o f a data transfer cycle. the other is a low - to - high transition on sdata while sdclk is high used to indicate the end of a data transfer cycle. data is always sent as complete 8 - bit bytes followed by an acknowledge generated. byte writing starts with a ?s tart? condition followed by 7 - bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. after successful reception of each byte, an ?acknowledge? (low) on the sdata wire will be generated by the c lock chip. controller can start to write to internal i 2 c registers after the string of data. the sequence order is as follows: bytes sequence order for i 2 c controller : clock address a(6:0) & r/w ack 8 bits dummy command code ack 8 bits dummy byte count ack byte0,1,2... until stop set r/w to 1 when ?ead back?, the data sequence is as follows : clock address a(6:0) & r/w ack byte 0 ack ack byte2, 3, 4... until stop byte 1
w83194br - 39b preliminary publication release date: june 2000 - 7 - revision 0.46 7.2 serial control registers the pin column lists the affected pin number and the @powerup column gives the default state at true power up. "command code" byte and "byte count" byte must be sent follow ing the acknowledge of the address byte. although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the sequence described below (register 0, register 1, register 2, ....) will be val id and acknowledged. frequency by software ssel5 ssel4 ssel3 ssel2 ssel1 ssel0 cpu(mhz) sdram(mhz) pci(mhz) 0 0 0 0 0 0 80.00 80.00 40.00 0 0 0 0 0 1 75.00 75.00 37.50 0 0 0 0 1 0 83.30 83.30 41.65 0 0 0 0 1 1 66.82 66.82 33.41 0 0 0 1 0 0 10 3.00 103.00 34.33 0 0 0 1 0 1 112.00 112.00 37.34 0 0 0 1 1 0 68.01 68.01 34.01 0 0 0 1 1 1 100.23 100.23 33.41 0 0 1 0 0 0 120.00 120.00 30.00 0 0 1 0 0 1 115.00 115.00 38.33 0 0 1 0 1 0 120.00 120.00 40.00 0 0 1 0 1 1 105.00 1 05.00 35.00 0 0 1 1 0 0 140.00 140.00 35.00 0 0 1 1 0 1 155.00 155.00 38.75 0 0 1 1 1 0 124.00 124.00 31.00 0 0 1 1 1 1 133.30 133.30 33.30 0 1 0 0 0 0 160.00 160.00 40.00 0 1 0 0 0 1 127.00 127.00 31.75 0 1 0 0 1 0 130.00 130.0 0 32.50 0 1 0 0 1 1 135.00 135.00 33.75 0 1 0 1 0 0 136.00 136.00 34.00 0 1 0 1 0 1 137.00 137.00 34.25 0 1 0 1 1 0 139.00 139.00 34.75 0 1 0 1 1 1 140.00 140.00 35.00 0 1 1 0 0 0 141.00 141.00 35.25 0 1 1 0 0 1 142.00 142.00 3 5.50 0 1 1 0 1 0 143.00 143.00 35.75
w83194br - 39b preliminary publication release date: june 2000 - 8 - revision 0.46 0 1 1 0 1 1 144.00 144.00 36.00 0 1 1 1 0 0 145.00 145.00 36.25 0 1 1 1 0 1 146.00 146.00 36.50 0 1 1 1 1 0 148.00 148.00 37.00 0 1 1 1 1 1 149.00 149.00 37.25 ssel5 ssel4 ssel3 ssel2 ssel1 sse l0 cpu(mhz) sdram(mhz) pci(mhz) 1 0 0 0 0 0 151.00 151.00 37.75 1 0 0 0 0 1 152.00 152.00 38.00 1 0 0 0 1 0 153.00 153.00 38.25 1 0 0 0 1 1 154.00 154.00 38.50 1 0 0 1 0 0 155.00 155.00 38.75 1 0 0 1 0 1 156.00 156.00 39.00 1 0 0 1 1 0 157.00 157.00 39.25 1 0 0 1 1 1 158.00 158.00 39.50 1 0 1 0 0 0 159.00 159.00 39.75 1 0 1 0 0 1 162.00 162.00 40.50 1 0 1 0 1 0 163.00 163.00 32.60 1 0 1 0 1 1 164.00 164.00 32.80 1 0 1 1 0 0 165.00 165.00 33.00 1 0 1 1 0 1 167.00 167.00 33.40 1 0 1 1 1 0 168.00 168.00 33.60 1 0 1 1 1 1 169.00 169.00 33.80 1 1 0 0 0 0 170.00 170.00 34.00 1 1 0 0 0 1 172.00 172.00 34.40 1 1 0 0 1 0 174.00 174.00 34.80 1 1 0 0 1 1 176.00 176.00 35.20 1 1 0 1 0 0 178 .00 178.00 35.60 1 1 0 1 0 1 180.00 180.00 36.00 1 1 0 1 1 0 182.00 182.00 36.40 1 1 0 1 1 1 184.00 184.00 36.80 1 1 1 0 0 0 186.00 186.00 37.20 1 1 1 0 0 1 188.00 188.00 37.60 1 1 1 0 1 0 190.00 190.00 38.00 1 1 1 0 1 1 192.00 192.00 38.40 1 1 1 1 0 0 194.00 194.00 38.80
w83194br - 39b preliminary publication release date: june 2000 - 9 - revision 0.46 1 1 1 1 0 1 196.00 196.00 39.20 1 1 1 1 1 0 198.00 198.00 39.60 1 1 1 1 1 1 200.00 200.00 40.00 7.2.1 register 0: cpu frequency select register (default = 0) bit @powerup pin description 7 0 - ssel5 (for frequency table selection by software via i 2 c) 6 0 - ssel4 (for frequency table selection by software via i 2 c) 5 0 - ssel3 (for frequency table selection by software via i 2 c) 4 0 - ssel2 (for frequency table selection by software via i 2 c) 3 0 - ssel1 (for frequency table selection by software via i 2 c) 2 0 - ssel0 (for frequency table selection by software via i 2 c) 1 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit 7:2 0 0 - 0 = running 1 = tristate all outputs 7. 2.2 register 1 : cpu , 48/24 mhz clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 1 - reserved 6 1 - reserved 5 0 - 0 = normal 1 = spread spectrum enabled 4 0 - 0 = 0.25% spread spectrum modulation 1 = 0.5% spread spectrum mod ulation 3 1 40 sdram12 (active / inactive) 2 1 - reserved 1 1 43 cpuclk1 (active / inactive) 0 1 44 cpuclk_f (active / inactive)
w83194br - 39b preliminary publication release date: june 2000 - 10 - revision 0.46 7.2.3 register 2: pci clock register (1 = enable, 0 = stopped) bit @powerup pin description 7 1 - reserved 6 1 7 pc iclk_f (active / inactive) 5 1 - reserved 4 1 14 pciclk4 (active / inactive) 3 1 12 pciclk3 (active / inactive) 2 1 11 pciclk2 (active / inactive) 1 1 10 pciclk1 (active / inactive) 0 1 8 pciclk0 (active / inactive) 7.2.4 register 3: sdram clock re gister ( 1 = enable, 0 = stopped ) bit @powerup pin description 7 1 46 ref1 (active / inactive) 6 1 2 ref0 (active / inactive) 5 1 26 48mhz (active / inactive) 4 1 25 24mhz (active / inactive) 3 1 47 ioapic (active / inactive) 2 1 21,20,18,17 sdram(8 :11) (active / inactive) 1 1 32,31,29,28 sdram(4:7) (active / inactive) 0 1 38,37,35,34 sdram(0:3) (active / inactive) 7.2.5 register 4: reserved register (1 = enable, 0 = stopped) bit @powerup pin description 7 1 - reserved 6 x - latched fs3# 5 x - latched fs2# 4 x - latched fs1# 3 x - latched fs0#
w83194br - 39b preliminary publication release date: june 2000 - 11 - revision 0.46 2 1 - reserved 1 1 - reserved 0 1 - reserved 7.2.6 register 5: reserved register bit @powerup pin description 7 1 - reserved 6 0 - reserved 5 0 - reserved 4 1 - reserved 3 0 - reserved 2 0 - re served 1 1 - reserved 0 1 - reserved 7.2.7 register 6~11: m/n step - less mode control registers 7.2.12 register 11: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 1 - winbond chip id 4 0 - winbond chip id 3 0 - winbond chip id 2 0 - winbond chip id 1 1 - winbond chip id 0 0 - winbond chip id 7.2.13 register 12: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 0 - winbond version id
w83194br - 39b preliminary publication release date: june 2000 - 12 - revision 0.46 2 0 - winbond version id 1 0 - winbond version id 0 1 - winbond version id
w83194br - 39b preliminary publication release date: june 2000 - 13 - revision 0.46 8.0 specifications 8.1 absolute maximum ratings stresses greater than those listed in this table may cause p ermanent damage to the device. precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. subjection to maximum conditions for extended periods may affect reliability. unused inputs mus t always be tied to an appropriate logic voltage level (ground or vdd). symbol parameter rating vdd , v in voltage on any pin with respect to gnd - 0.5 v to + 7.0 v t stg storage temperature - 65 c to + 150 c t b ambient temperature - 55 c to + 125 c t a operating temperature 0 c to + 70 c 8.2 ac characteristics vdd = vddq3 = 3.3v 5 %, vddq2 = vddl1=vddl2 = 2.375v~2.9v , t a = 0 c to +70 c parameter symbol min typ max units test conditions output duty cycle 45 50 55 % measured at 1.5v cpu/sdram to pci offset t off 1 2.6 4 ns 15 pf load measured at 1.5v skew (cpu - cpu), (pci - pci), (sdram - sdram) t skew 250 ps 15 pf load measured at 1.5v cpu/sdram cycle to cycle jitter t ccj 250 ps cpu/sdram absolute jitter t ja 500 ps jitter spectrum 20 db b andwidth from center bw j 500 khz output rise (0.4v ~ 2.0v) & fall (2.0v ~0.4v) time t tlh t thl 0.4 1.6 ns 15 pf load on cpu and pci outputs overshoot/undershoot beyond power rails v over 0.7 1.5 v 22 w at source of 8 inch pcb run to 15 pf load ring back exclusion v rbe 0.7 2.1 v ring back must not enter this range.
w83194br - 39b preliminary publication release date: june 2000 - 14 - revision 0.46 8.3 dc characteristics vdd = vddq3 = 3.3v 5 %, vddq2 = vddl1=vddl2 = 2.375v~2.9v , t a = 0 c to +70 c parameter symbol min typ max units test conditions input low voltage v il 0.8 v dc input high voltage v ih 2.0 v dc input low current i il - 66 m a input high current i ih 5 m a output low voltage i ol = 4 ma v ol 0.4 v dc all outputs output high voltage i oh = 4ma v oh 2.4 v dc all outputs using 3.3v power tri - state leakage cu rrent ioz 10 m a dynamic supply current for vdd + vddq3 i dd3 ma cpu = 66.6 mhz pci = 33.3 mhz with load dynamic supply current for vddq2 + vddq2b i dd2 ma same as above cpu stop current for vdd + vddq3 i cpus3 ma same as above cpu stop curr ent for vddq2 + vddq2b i cpus2 ma same as above pci stop current for vdd + vddq3 i pd3 ma
w83194br - 39b preliminary publication release date: june 2000 - 15 - revision 0.46 8.4 buffer characteristics 8.4.1 type 1 buffer for cpu clock parameter symbol min typ max units test conditions pull - up current min i oh(min) - 27 ma vou t = 1.0 v pull - up current max i oh(max) - 27 ma vout = 2.0v pull - down current min i ol(min) ma vout = 1.2 v pull - down current max i ol(max) 27 ma vout = 0.3 v rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load 8.4.2 type 2 buffer for ioapic parameter symbol min typ max units test conditions pull - up current min i oh(min) ma vout = 1.4 v pull - up current max i oh(max) - 29 ma vout = 2.7 v pull - down curren t min i ol(min) ma vout = 1.0 v pull - down current max i ol(max) 28 ma vout = 0.2 v rise/fall time min between 0.7 v and 1.7 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.7 v and 1.7 v t rf(max) 1.8 ns 20pf load
w83194br - 39b preliminary publication release date: june 2000 - 16 - revision 0.46 8.4.3 type 3 buffer f or ref1, 24mhz, 48mhz parameter symbol min typ max units test conditions pull - up current min i oh(min) - 29 ma vout = 1.0 v pull - up current max i oh(max) - 23 ma vout = 3.135v pull - down current min i ol(min) 29 ma vout = 1.95 v pull - down current max i ol(max) ma vout = 0.4 v rise/fall time min between 0.8 v and 2.0 v t rf(min) 1.0 ns 10pf load rise/fall time max between 0.8 v and 2.0 v t rf(max) 4.0 ns 20pf load 8.4.4 type 4 buffer for sdram (0:12) parameter symbol min typ max units test condi tions pull - up current min i oh(min) ma vout = 1.65 v pull - up current max i oh(max) - 46 ma vout = 3.135 v pull - down current min i ol(min) ma vout = 1.65 v pull - down current max i ol(max) 53 ma vout = 0.4 v rise/fall time min between 0.8 v and 2.0 v t rf(min) 0.5 ns 20pf load rise/fall time max between 0.8 v and 2.0 v t rf(max) 1.3 ns 30pf load 8.4.5 type 5 buffer for pciclk(0:4,f) parameter symbol min typ max units test conditions pull - up current min i oh(min) - 33 ma vout = 1.0 v pull - up current max i oh(max) - 33 ma vout = 3.135 v pull - down current min i ol(min) 30 ma vout = 1.95 v pull - down current max i ol(max) 38 ma vout = 0.4 v rise/fall time min between 0.8 v and 2.0 v t rf(min) 0.5 ns 15pf load rise/fall time max between 0.8 v and 2.0 v t rf(max) 2.0 ns 30pf load
w83194br - 39b preliminary publication release date: june 2000 - 17 - revision 0.46 9.0 operation of du al fuction pins pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this device (see pin description). during power up, these pins are in input mode (see fig1), therefore, and are considered input select pins. when vdd reaches 2.5v, the logic level that is present on these pins is latched into their appropriate internal registers. once the correct information is properly latched, these pins will change into output pins and will be pulled low by default. at the end of the power up timer (within 3 ms) outputs starts to toggle at the specified frequency. within 3ms input output output tri-state output pull-low 2.5v output tri-state output pull-low #7 pciclk_f/mode #46 ref1/fs2 #25 24/fs1 #26 48/fs0 all other clocks vdd each of these pins has a large pull - up resistor ( 250 k w @3.3v ) insid e. the default state will be logic 1, but the internal pull - up resistor may be too large when long traces or heavy load appear on these dual function pins. under these conditions, an external 10 k w resistor is recommended to be connected to vdd if logic 1 is expected. otherwise, there should be direct connection to ground if a logic 0 is desired. the 10 k w resistor should be placed before the serious terminating resistor. note that these logic will only be latched at initial power on. if optional emi re ducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. these capacitors have typical values ranging from 4.7pf to 22pf.
w83194br - 39b preliminary publication release date: june 2000 - 18 - revision 0.46 device pin vdd ground ground 10k series terminating resistor clock trace emi reducing cap 10k w w optional device pin vdd pad ground pad programming header series terminating resistor clock trace emi reducing cap ground 10k w optional
w83194br - 39b preliminary publication release date: june 2000 - 19 - revision 0.46 10.0 ordering infor mation part number package type production flow w83194br - 39b 48 pin ssop commercial, 0 c to +70 c 11.0 how to read th e top marking 1st line: winbond logo and the type number: w83194br - 39b 2nd line: tra cking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 814 g b b 814 : packages made in ' 98 , week 14 g : assembly house id; a mea ns ase, s means spil, g means gr b : winbond internal use code a : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . w83194br - 39b 28051234 814gba
w83194br - 39b preliminary publication release date: june 2000 - 20 - revision 0.46 12.0 package drawin g and dimensions headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 ple ase note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support applian ces, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbon d for any damages resulting from such improper use or sale.

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